* Programmable CAS Latencies (3, 4 and 5), Burst Length (4 & 8) and Burst Type
* Auto Refresh (CBR) and Self Refresh
* Average Refresh Period 7.8 µs at a T lo.

devices and a PLL for the clock distribution. This reduces capacitive loading to the system bus, but adds one cycle to the SDRAM timing. Decoupling capacitors are mounted on the PCB board. The DIMMs feature serial presence detect based on a serial E².

HYS72T64020HR

HYS72T64020HU

HYS72T64020GR

HYS72T64020GR-3-A

HYS72T64020GR-37-A

HYS72T64020GR-5-A

HYS72T64000

HYS72T64000GR

HYS72T64000GR-37-A

HYS72T64000GR-5-A

HYS72T64000GU

HYS72T64000GU-37-A

HYS72T64000GU-5-A